This invention relates generally to data compression and more particularly to data decompression.
Processing of video data is known to include receiving a stream of video data and rendering it such that it may be presented on a display device. The video stream includes a plurality of video frames and/or fields. Typically, video frames are generated for display on a progressive display devices, such as CRT monitors, High Definition Televisions, and/or LCD panels, while video fields are typically displayed on interlaced devices such as television sets. For each video framie, or video field, the video data includes information regarding the object-elements (e.g., triangles) that make up the image(s) being rendered. For example, the information may be vertex data of the triangles that includes physical coordinates, texture coordinates, color information/or alpha-blending information and/or other information needed to render the triangles.
In a computer system, a video graphics processor is operably coupled to receive an uncompressed stream of video data from a central processing unit and/or a video input device, such as a television decoder. Upon receiving the strewn of video data, the video graphics processor produces pixel data therefrom and provides the pixel data to the display device. The video graphics processor produces the pixel data by interpreting the object-element parameters, generating pixel data for each pixel of an object-element, and storing the pixel data in a frame buffer until a full frame of data is stored. Such processing is usually done in accordance with the refresh rate of the display, which is typically 50 hertz, 60 hertz, 75 hertz, 90 hertz, etc.
A video graphics processor may also process compressed video data that has been compressed in accordance with the Motion Picture Expert Group (MPEG) 2 standard. In general, the MPEG 2 standard compresses a video frame by encoding the difference between a current video frame and reference video frames. As is known, MPEG 2 provides three types of video frames, an I frame, a P frame, and a B frame. The I frame is an independent frame and is compressed independent of other frames. The P frame is compressed based on differences between it and a reference I frame. The B frame is compressed based on the differences between it, a reference P frame and a reference I frame.
The MPEG 2 standard also prescribes an architecture for an MPEG 2 video decoder. Such a decoder includes a variable length decoding section, inverse scan section, inverse quantization, inverse discrete cosine transform section, motion compensation section, and memory. The implementation of the architecture prescribed by the MPEG 2 standard is costly, in part, due to the cost of the inverse discrete cosine transform function. Such a function typically requires several separate memory sections to properly process the inverse discrete cosine transform function. Such additional memory requires substantial die area, which increase the cost of implementing the decoder on an integrated circuit.
Decoding of MPEG 2 encoded video data typically is implemented in software, which is executed by a central processing unit of a computer, and a hardware co-processor, such as a video graphics circuit. The software portion typically includes parsing of the compressed video data into an audio component, a video component, a subpicture component, and an auxiliary component. The video component is provided to a software variable length decoder, which produces motion vectors and run/level data. The run/level data is provided to a dequanitizing software module and the dequantized data is provided to system memory. The video graphics circuitry retrieves the motion vectors and the run/level data from system memory and performs a run-level decode, dequantization, de-zigzagging of the coefficients, and an inverse discrete cosine transform function. Once the error terms have been recaptured, the video graphics circuit utilizes the motion vectors and the error terms to recapture the uncompressed video data.
In such an embodiment, the software portion of the video decoding process is very much dependent on the hardware portion of the decoding module. As such, the software portion executes a certain number of instructions then waits for the hardware co-processor to execute its related functions. While the hardware portion is executing its functions, the software portion is waiting. The alternate performance of the respective functions between the software and the hardware continues until all of the video has been processed. As such, the hardware waits for the software to perform its function and then the software waits while the hardware is performing its function. When the software is waiting, it directly corresponds to the central processing unit waiting. While the central processing unit may perform other functions while waiting for the video graphics hardware, it still must monitor the hardware to know when the next software function is to be performed.
Therefore, a need exists for a method and apparatus for data decompression that improves concurrency between software portions and hardware portions of the data decompression process and reduces the memory required for such processing.